SYNTEL PROJECT

Simulog, Cadence Design Systems, École des Mines de Paris, INRIA and Thomson CSF Comsys have been chosen by the RNRT (French Network of Research in Telecommunication) to carry out the SYNTEL project.
The objective of this project is the development of a hardware/software co-design platform for developping wireless protocols.
The SYNTEL project positions Esterel Studio as a tool for developping System-On-a-Chip-based architectures (SOCs). Esterel Studio will be connected to VCC, the co-design environment from Cadence, which has been chosen by Esterel users such as Thomson CSF, Texas Instruments, Motorola, etc.
Within the scope of this project, the ECL specification language (Esterel C Language) will be intregrated to Esterel Studio.
Developped by Cadence, ECL allows to specify the control part of an application in Esterel, while the data manipulation part is written in C. Esterel Studio, connected to VCC, will be used by Comsys to design mobile communication systems in the framework of UMTS. EDA (Electronics Design Automation) is now facing a important challenge with SOC design, with the absolute priority of reducing Time-To-Market.
This reduction implies co-design, the use of formal methods and IP re-use.